The present invention relates to the field of phase locked loop (PLL) circuits, and more particularly to PLLs utilized in frequency synthesizers for wideband tuner applications, such as for example, satellite, cable, or terrestrial TV tuner applications.
There exist a large variety of PLL architectures. One way of classifying them is based on the type of controlled oscillator type. There are voltage controlled oscillator based PLLs and current controlled oscillator based PLLs. Another way of classifying the PLLs is based on the type of loop filter. There are passive RC or active loop filters and voltage-mode or current-mode loop filters. Also the PLLs can be classified as a function of the method used to generate the stabilizing zero. There are RC time constant based PLLs and feed-forward based PLLs.
FIGS. 1a–1d present some examples of prior art PLL architectures. FIG. 1a shows a passive RC loop filter PLL using a voltage controlled oscillator. FIG. 1b shows a passive RC loop filter PLL using a current controlled oscillator. FIG. 1c presents an example of a feed-forward loop filter using a voltage controlled oscillator while FIG. 1d shows an example of a feed-forward loop filter PLL using a current controlled oscillator.
A typical PLL loop (for example PLLs 100a–d as shown in FIGS. 1a–1d) consists of a reference oscillator that provides an input reference clock 102, the phase frequency detector 104 (PFD) that compares the reference clock with the feedback clock, the charge-pump 106 (CP) that injects a positive or negative current in the loop filter 108 (LF) based on the direction of the phase difference between the two input clocks, the loop filter 108 (that can be passive or active, without or with feed-forward loop) that ensures the loop stability, the controlled oscillator 110 (voltage controlled VCO or current controlled ICO) and the feedback divider 112 (N) that sets the output clock frequency (fout=N*fref).
The time constants and settling behavior of a PLL are dependent on physical elements (resistors, capacitors, currents, etc) that may have a significant variation over process, temperature and supply voltage. Furthermore in variable output frequency synthesizers the natural frequency, loop bandwidth and damping factor are dependent on the feedback divider modulus (usually denoted with N).
The system level specifications typically impose restrictions on the loop bandwidth, jitter peaking and transient overshoot and settling time. Another critical parameter for the output clock jitter performance is the loop damping factor, that is intrinsically related to the feedback loop phase margin and describes the stability of the entire feedback system.
During the integrated circuit fabrication all of these PLL parameters will vary in a certain range and they may impact the performance of the circuit if they exceed some limit ranges. Many applications require a constant loop bandwidth and damping factor over the entire output frequency range, which means over the entire range of the feedback divider modulus (N). Thus, a divider modulus independent loop bandwidth and damping factor PLL architecture is required.
For example, in the case of a charge-pump PLL using a standard passive RC loop filter and a voltage controlled oscillator (VCO), the natural frequency (ωn), ripple filtering pole (ωp), damping factor (ξ), loop bandwidth (ωc), ripple pole frequency (ωp) and pole-zero separation (p/z) are given by the following equations:
                              ω          n                =                                            Kvco              ·              Icp                                      2              ⁢                                                          ⁢                              π                ·                N                ·                Ci                                                                        (        1        )                                          ω          z                =                  1                      R            ·            Ci                                              (        2        )                                ξ        =                                            1              2                        ·                                          ω                ⁢                                                                  ⁢                n                                            ω                ⁢                                                                  ⁢                z                                              =                                    R              2                        ⁢                                                            Kvco                  ·                  Icp                  ·                  Ci                                                  2                  ⁢                                                                          ⁢                                      π                    ·                    N                                                                                                          (        3        )                                          ω          c                =                                            ω              ⁢                                                          ⁢                              n                2                                                    ω              ⁢                                                          ⁢              z                                =                                    R              ·              Kvco              ·              Icp                                      2              ⁢                                                          ⁢                              π                ·                N                                                                        (        4        )                                          ω          p                =                              1                          R              ·                                                Cp                  ·                  Ci                                                  Cp                  +                  Ci                                                              ≈                      1                          R              ·              Cp                                                          (        5        )                                          p          /          z                =                                            ω              ⁢                                                          ⁢              p                                      ω              ⁢                                                          ⁢              z                                =                                    Ci                                                Cp                  ·                  Ci                                                  Cp                  +                  Ci                                                      ≈                          Ci              Cp                                                          (        6        )            where Kvco is the oscillator gain, Ci is the integration capacitor, Cp is the ripple pole capacitor, R is the stabilizing zero resistance, N is the feedback divider modulus and Icp is the charge-pump current.
In most semiconductor fabrication processes (e.g. CMOS, bipolar or BICMOS processes) the on-chip resistance and capacitance variation over the worst case process corners is around ±20%. Also depending on the way in which the charge-pump current is generated it can have a variation up to ±25%. In the case that the oscillator is a ring oscillator, the oscillator gain is dependent finally also on some type of capacitance (that is charged and discharge every cycle) and the equivalent resistor through which the charging and discharging is performed if a constant voltage is applied or the equivalent constant current that charges and discharges that capacitance. Thus the oscillator gain can have as much as ±40% variation over the worst case corners. In the LC oscillator case, the gain depends on the tank inductance and capacitance value and also on the transconductance of the oscillator amplifier. In this case the gain may have a lower process variation, but still can be as high as ±20%.
During integrated circuit processing the different elements that influence the loop bandwidth and stability may result in corners that produce a cumulative variation of the loop parameters (either on the positive or negative side). Therefore variations as large as 100% can result if no measures to compensate the process variation are taken. For example if a PLL is designed to have a typical damping factor of ξ=1 in the nominal process corner, it may vary after process fabrication having a damping factor between 0.5 and 2, resulting in a drastically different peaking and settling time performance. Similarly, process variation may appear on other critical PLL loop specifications such as loop bandwidth, overshoot, peaking, settling time, etc. This uncertainty in the PLL performance leads to a poorly behaved design.
One solution to overcome the performance degradation due to process and temperature variation of the on-chip components is to allow in the design phase enough margins such that even in the worst case corners the critical specifications do not go outside the recommended range for proper operation of the PLL. The main drawback of this solution is that a suboptimal design results because of the large margins that need to be built-in in order to compromise between the contradicting PLL specifications (e.g. good stability requires a higher value of the damping factor and this results in a higher settling time).
Another solution to overcome the PLL performance variations is to try to compensate them by building a process, temperature and even a divider modulus independent PLL architecture.
Several architectures have been proposed to ensure a partial or even a fully independence of the PLL performance on the process temperature and divider modulus corners.
A wide spread solution to achieve a process independent PLL is to use a self biasing technique. It consists in using as charge-pump current a fraction of the current that drives the oscillator. In this way the Kvco*Icp term results virtually process independent. For feed-forward loop filter PLLs the loop bandwidth and the damping factor result dependent on ratios of capacitors that track well over process and thus have a high process independence. In the case of a passive RC filter in which the stabilizing zero is set with an on chip series resistor, this should be calibrated to a fixed value (e.g. using an off-chip high precision resistor) in order to achieve the process independence of the damping factor. The main drawback of the self-biasing technique is that it adds one more feedback loop to the system that may result in start-up or nonlinear stability issues. Thus, extra circuitry needs to be used to avoid these problems, increasing the complexity of the design. Furthermore, generally the self-biasing technique can be applied only to the ring oscillator based PLLs where the oscillator current gives an indication of the oscillator gain. This is not the case for the LC oscillator where the gain is practically independent of the current through the active devices of the amplifier (Kvco has only a very weak dependence on gm of the active device).
An alternative solution to compensate the process variation is to use a bandgap referencing technique. It consists of relating some of the elements that appear in the damping factor and loop bandwidth expressions to the bandgap voltage that has a very low process and temperature variation.
Taking again the example of the passive RC loop filter PLL, if the charge-pump current is made inverse proportional to the square of the on-chip resistor value (Icp=Vbg/Rbg2), where Vbg is the bandgap voltage and Rbg is the bandgap resistance, than the damping factor results proportional to √Vbg·R/Rbg. If the loop filter resistance (R) is built with the same unit resistance as the bandgap resistance (Rbg) and uses the same orientation, then they will track each other over process and their ratio (R/Rbg) will have virtually no process and temperature variation.
In the case of ring oscillators, the oscillator gain is inverse proportional to the total capacitance at the output of each ring inverter. This capacitance is usually dominated by the gate capacitance of the devices from the active inverter stage. If the loop filter uses MOS capacitors of the same type with the one used in the oscillator ring inverter, then they will track reasonably well over process and temperature and the Kvco*Ci term will become almost process independent.
A major drawback of this architecture is that while the damping factor results process independent, the loop bandwidth has a strong process variation due to the 1/Rbg term. Furthermore in many PLLs the loop filter capacitor cannot be made of the same device type as the ring oscillator active devices. One example is when the oscillator operates at GHz range and needs to use deep-submicron devices, while the loop filter needs to use thick oxide devices to minimize the gate leakage current that would otherwise degrade the reference spurs performance. Thus the damping factor will have a residual process variation given by √{square root over (Kvco·Ci)}=√{square root over (Ci/Cvco)} which can have as large as ±25% variation depending on the oscillator and loop filter capacitor types.
A similar bandgap referencing process independent architecture can be applied to the feed-forward PLL case using a voltage controlled oscillator. The natural frequency (ωn), ripple filtering pole (ωp), damping factor (ξ), loop bandwidth (ωc) and pole-zero separation (p/z) are given by the following equations:
                              ω          n                =                                                            Kvco                ·                Icpi                ·                gmi                                            2                ⁢                                                                  ⁢                                  π                  ·                  N                  ·                  Ci                                                              =                                                    Kvco                ·                Icpi                                            2                ⁢                                                                  ⁢                                  π                  ·                  N                  ·                  Ci                  ·                  Ri                                                                                        (        7        )                                          ω          z                =                                            Icpp              Icpi                        ·                          gmi                              kip                ·                Ci                                              =                                    Icpp              Icpi                        ·                          1                              Ri                ·                kip                ·                Ci                                                                        (        8        )                                ξ        =                                            1              2                        ·                                          ω                ⁢                                                                  ⁢                n                                            ω                ⁢                                                                  ⁢                z                                              =                                                    kip                2                            ·                              Icpp                Icpi                                      ⁢                                                            Kvco                  ·                  Icp                  ·                  Ci                  ·                  Ri                                                  2                  ⁢                                                                          ⁢                                      π                    ·                    N                                                                                                          (        9        )                                          ω          c                =                                            ω              ⁢                                                          ⁢                              n                2                                                    ω              ⁢                                                          ⁢              z                                =                                    Ri              ·              Kvco              ·              Icpp                                      2              ⁢                                                          ⁢                              π                ·                N                                                                        (        10        )                                          ω          p                =                  1                      Rp            ·            Cp                                              (        11        )                                          p          /          z                =                                            ω              ⁢                                                          ⁢              p                                      ω              ⁢                                                          ⁢              z                                =                                    Icpp              Icpi                        ·                                          Rp                ·                Cp                                            Ri                ·                kip                ·                Ci                                                                        (        12        )            where Kvco is the oscillator gain, Ci is the integration capacitor, Cp is the ripple pole capacitor, gmi is the integral path transconductance, Ri is the integral path degeneration resistance, Rp is the ripple pole resistance, Kip is the proportional path current gain, N is the feedback divider modulus and Icpi and Icpp are the integral and proportional charge-pump currents.
The kip current gain is given usually by a current mirror that has a very low process dependence, and the ratio of the two charge-pump currents has also a very small process variation. If the charge-pump current is generated from a bandgap voltage using a V-to-I converter (Icp=Vbg/Rbg) than the Icpi*Ri=Vbg*Ri/Rbg has virtually no process variation (assuming that Ri and Rbg are reasonably matched). As the Kvco*Ci term has also a very low process variation, then the damping factor has a low process variation, while the loop bandwidth has only a moderate process variation due to the Kvco oscillator gain.
The main drawback of this solution is that it can be applied only to the current controlled oscillator based PLLs and not to the voltage controlled oscillator based PLLs.
To achieve the feedback divider modulus independence several solutions have been proposed in the past. They involve the variation of one of the elements from the damping factor expression (capacitor, resistor or current) such that it compensates for the N modulus variation.
One solution is to change the charge-pump current (called charge-pump switching architecture), in which Icp is made proportional to N and thus the Icp/N term becomes independent of N. As Icp and N appear in the damping factor and loop bandwidth expressions in the same position (at numerator respectively at the denominator) the charge-pump current switching ensures both the damping factor and loop bandwidth N independence. The drawback of this technique is the increased ripple on the oscillator control signal due to the increased parasitic switching effects that appear at larger charge-pump currents (clock injection and channel charge sharing). This is particularly troublesome in the wide frequency range PLLs that require a large loop bandwidth. In this case, the charge-pump needs to vary over a wide range to compensate the N change and also needs to be rather high to ensure the high bandwidth. The increased ripple on the oscillator control signal leads to elevated reference spurs levels which are of great concern in the frequency translation PLLs.
An alternative solution is to change the loop filter integral capacitance (Ci) directly proportional to the N modulus (named capacitor switching technique). Ci is varied such that the Ci/N term becomes N independent and thus the damping factor results N independent. To achieve an N independent pole-zero separation the ripple pole capacitance (Cp) needs to be switched also proportional to the N feedback divider modulus. The advantage of this architecture is the preservation of the good reference spurs performance over the entire output frequency range (a low charge-pump current value is used). The drawback is the large variation of the loop bandwidth with the N modulus (Ci does not influence the loop bandwidth) and the relatively large loop filter capacitor value, particularly in the wide frequency range applications). The large loop filter area may also be a concern in the case of mixed analog-digital chips where a larger area increases the sensitivity to substrate noise coupling.
The existing process and temperature independent PLL architectures belong to the closed-loop architecture category in which the PLL feedback loop is always kept active. The advantage of this approach is that it does not need additional time for the calibration process. The calibration is done either continuous or a-priori. The self-biasing technique is a continuous time closed loop architecture in which the charge-pump current is permanently changed by the additional feedback loop to compensate the on-chip element variation. The advantage of the continuous time element variation is that it can compensate also for the dynamic temperature variations. The bandgap referencing technique is also a closed loop calibration method using an a-priori tuning in which no measurements (feedback control) are done. The loop elements are tuned based on a bandgap voltage value that resides outside the PLL loop and can be at a large distance from the PLL and thus may operate at drastically different temperature. Therefore the bandgap referencing technique is more sensitive to the temperature variation of the loop elements.
In most applications the process variation of the on-chip element values (±20 . . . ±25%) is much larger than the temperature variation (±1 . . . ±3%) so process variations are the dominant factor.
It is therefore desirable to provide a PLL that overcomes some or all of the problems described above to provide a process, temperature and divider modulus independence for the loop bandwidth and damping factor.